Designers of computer circuit boards contend with constraints relating to the length and path of lines connecting the various chips on the circuit board. In many circuit board applications there is a need to have data arrive at various chips at the same time during a data transfer. As the speed and data transfer rates increase and the size of chips decrease, this problem becomes more pronounced. Designers of computer memory boards are particularly hard pressed to assure that the data, address and control lines have uniform length between the memory chips and the various control chips. To ensure that data arrives at one chip in sync with data arriving at other chips, designers are often constrained to design data paths that are not the most direct path.
FIG. 1 provides a view of a typical computer memory board 10. In the typical memory board 10, memory chips 17 are arrayed in a linear pattern with control chips 19 located near the center. In order to assure that data is transferred on and off of the board in a coordinated pattern, the data lines from all of the chips to the control chip at the center of the board must be of approximately equal length. Thus, the lines connecting the outer most chips 17A must be the same lengths as the lines connecting the inner chips 17B. This need to have substantial uniformity in the length of the lines from all of the memory chips 17, whether they are the outer chips 17A, the inner chips 17B or otherwise, complicates the design and function of the board 10. The extra long lines in the current configuration waste precious board space and generate unnecessary and problematic heat. Furthermore, the lines to memory chips 17B that are close to the control chip 19 may require the line to zig zag back and forth in order to increase the path length.